In the prior art, a common chip packaging technology mainly includes the following processes. First, the active surface of the chip is adhered to the substrate wafer by an adhesive tape and plastic-packaged on wafer level, and the substrate wafer is detached. Then, a rewiring layer is formed by performing rewiring on the active surface of the chip, and solder balls are planted. Finally, the package body is cut into single pieces. In this packaging technology, an adhesive tape is used for the adhering, and the adhesive force thereof is difficult to be ensured under the high temperature in the plastic packaging. As a result, the chip will be displaced under the impact of the plastic packaging material mold flow during the plastic packaging, and thus the subsequent rewiring process is affected. Therefore, the packaging process is difficult to control and the yield is not high. In addition, the chip is directly embedded in the plastic package body. Due to the different thermal expansion coefficients of the chip and the plastic package body, stress will be certainly caused by the temperature changes and thus the wafer is prone to warp greatly, thereby affecting the reliability of the package product. On the other hand, during use, due to the presence of the stress, the chip is also likely to be displaced or fall off, thereby affecting the reliability of the package product in use.